Recently, an analog switch circuit has been increasingly used in A/D converters, D/A converters, and sample-and-hold circuits, for example; such an analog switch circuit is generally formed in small shape in order to increase controllability and characteristics, or to minimize power consumption.
With the analog switch circuit, there exists an offset voltage; when the offset voltage is high, the operating point of the switch varies, thus adversely affecting the accuracy of the A/D converters, D/A converters, and sample-and-hold circuits that employ the analog switch circuit.
So, the analog switch circuit typically includes an additional offset cancellation circuit for canceling the offset voltage generated by the analog switch circuit.
Conventionally, an offset cancellation circuit 10 as shown in FIG. 3 exists as an offset cancellation circuit for an analog switch to cancel the offset voltage of the analog switch circuit.
FIG. 3 is a circuit diagram depicting a prior art offset cancellation circuit 20 applied to the analog switch circuit 10.
In FIG. 3, the analog switch 10 comprises an N-channel MOS transistor 11 and a P-channel MOS transistor 12 that input drive signals .o slashed. and .o slashed. (an inverted version of the drive signal .o slashed. is hereinafter referred to as .o slashed.) to their gate terminals, respectively.
The offset cancellation circuit 20 comprises a P-channel MOS transistor 21 having approximately half the size of the P-channel MOS transistor that comprises the analog switch circuit 10, and an N-channel MOS transistor 22 having approximately half the size of the N-channel MOS transistor 11 that comprises the analog switch circuit 10.
The P-channel MOS transistor 21 having its gate terminal connected commonly to the gate terminal of the N-channel MOS transistor 11 of the analog switch circuit 10, and having its source and drain terminals connected to each other and also connected to an output terminal of the analog switch circuit 10; similarly, the N-channel MOS transistor 22 has its gate terminal connected commonly to the gate terminal of the P-channel MOS transistor 12 of the analog witch circuit 10, and having its source and drain terminals connected to each other and also connected to the output terminal of the analog switch circuit 10.
So configured, when a logic high ("H") is applied to the analog switch circuit 10 as the drive signal .o slashed., a "H" is applied to the gate terminal of the N-channel MOS transistor 11, while a logic low ("L") is applied to the gate terminal of the P-channel MOS transistor 12, so the analog switch circuit 10 turns on, causing the voltage signal inputted from the input terminal Vin to be outputted at the output terminal Vout. When a "L" is outputted to the analog switch circuit 10 as the drive signal .o slashed., a "L" is applied to the gate terminal of the N-channel MOS transistor 11, while a "H" is applied to the gate terminal of the P-channel MOS transistor 12, so the analog switch circuit 10 turns off.
Here, for the offset voltage components induced by variations in input voltage of the analog switch circuit 10, an offset voltage component caused by the N-channel MOS transistor 11 is absorbed by capacitance of the N-channel MOS transistor 22, while an offset voltage component caused by the P-channel MOS transistor 12 is absorbed by capacitance of the P-channel MOS transistor 21. Thus, the offset voltage generated in the analog switch circuit 10 can be reduced.
However, with such an offset cancellation circuit for an analog switch, the offset voltage might be reduced, but the cancellation of the offset voltage is insufficient for some applications, so there is a need for further reduction in offset voltage.
A specific example is discussed below with reference to FIG. 4.
FIG. 4 is a schematic circuit diagram depicting a comparator portion in an A/D converter for explaining the problem of the prior art example, where it is assumed that the reference voltage margin is 2 V and applied to an analog switch circuit in a 10-bit A/D converter.
Recently, equipment that handles high-quality image data, such as HDTV (High Definition Television) and portable camcorders, demands higher resolution and more sophisticated image data processing; for such apparatus that handle high resolution of image data, more sophisticated A/D converters, more specifically, A/D converters with about 10 bits (=1024) of accuracy, are required.
That is, with the A/D converter as described above, in order to secure 10 bits of accuracy, the voltage steps divided by resistance R are less than 2 mV (2 V divided by 1024), which means that if an offset voltage greater than that occurs, 10 bits of accuracy could not be secured. Especially, in the example shown in FIG. 4, the offset voltage of the analog switch circuit used at the input terminal of the comparator 30 is found to affect the overall characteristics.
However, the prior art offset cancellation circuit 20 for the analog switch cancels the offset voltage insufficiently, so an offset voltage of about up to .+-.8 mV is present, as shown in FIG. 2. This could merely secure 8 bits of accuracy, thus preventing use in high-accuracy circuits.
Accordingly, it is an object of the present invention to provide an offset cancellation circuit for an analog switch that substantially reduces the offset voltage induced by the analog switch circuit.